With the rapid development of digital synchronous network, the requirement to reliability and security of clocks in a communication apparatus has become higher and higher.
The so-called network synchronization means that the clock frequencies and phases of all switching nodes in the network are controlled in a predetermined range of tolerance, so that all the digital streams of each switching node within the network are correctly and effectively switched, otherwise, overflow and underflow of information bits may be generated in a digital switch, sliding damage of digital streams and errors of data may be caused. Since the sliding due to non-synchronous clock frequencies may occur in all the systems which use a same clock, it has great influence and must be controlled effectively.
In the communication apparatus, hot backup protection is usually employed for a clock unit, and there are a plurality of clock reference sources for the clock unit, so as to ensure that the switching of the clock sources and of the clock units can be triggered in time when a clock operates abnormally, and therefore it is especially important to check the validity of clocks. However, in the existing methods for clock validity checking, some checking circuits may use some separated apparatuses on periphery, which will take much space (comprising layout space and wiring space) of a printed circuit board (PCB) and occupy large resources.